The present invention relates to a driving system for driving a plasma display panel (PDP) of a matrix display type.
The applicant of the present invention submitted a driving method for a PDP disclosed in Japanese Patent Application No. 7-90977. In the method, an address margin is largely improved, thereby obtaining an accurate luminous display without error discharge.
FIG. 14 shows a display system in the prior art. The display system comprises a sync signal separation circuit 1 applied with a video signal for extracting horizontal and vertical synchronizing signals. The horizontal and vertical synchronizing signals are applied to a timing pulse generating circuit 2 which produces various timing pulses based on the synchronizing signals. The timing pulses are applied to an A/D converter 3, a memory control circuit 5, and a read-out timing pulse generating circuit 7.
The A/D converter 3 is further applied with the video signal and operated to convert the input video signal into a digital pixel data signal for each pixel in synchronism with the timing pulse. The digital pixel data signal is applied to a frame memory 4.
The memory control circuit 5 produces a writing signal and a reading signal in synchronism with the timing pulse. The writing and reading signals are applied to the frame memory 4. The frame memory 4 is operated to store the pixel data from the A/D converter 3 in order in response to the writing signal, and to read the pixel data stored therein in order in response to the reading signal. The read pixel data is applied to an output processing circuit 6.
The read-out timing pulse generating circuit 7 generates various read-out timing pulses for controlling the discharge and emission of light. The read-out timing pulses are applied to a row electrode driver 10 and the output processing circuit 6. The output processing circuit 6 applies the pixel data from the frame memory 4 to a pixel data electrode driver 12 in synchronism with the read-out timing pulse.
The pixel data electrode driver 12 is connected to pixel data electrodes D1, D2, D3, . . . Dm-1, and Dm of a plasma display panel (PDP) 11. The pixel data electrode driver 12 produces a pixel data pulse DP corresponding to the pixel data from the output processing circuit 6 and applies the pixel data pulse DP to the pixel data electrodes D1-Dm for driving the pixel data electrodes.
The row electrode driver 10 is connected to a series of row electrodes X1, X2, X3, . . . Xn and another series of row electrodes Y1, Y2, Y3, . . . Yn of the PDP 11. The row electrode driver 10 produces reset pulses RPx and RPy for forcibly exciting to discharge a pair of row electrodes X and Y for producing charged particles in a discharge space, which will be described hereinafter, a priming pulse PP for reproducing the charged particle, a scanning pulse SP for writing the pixel data, sustaining pulses IPx and IPy for sustaining the discharge and emission of light, and an erasing pulse EP for erasing wall charge. These pulses are applied to the row electrodes X1-Xn and Y1-Yn of the PDP 11 at the respective timings corresponding to the read-out timing pulses from the read-out timing pulse generating circuit 7.
FIG. 15 shows the PDP 11. The PDP 11 comprises a front glass substrate 110 as a display portion. On the front substrate 110, the row electrodes X1-Xn and Y1-Yn are alternately formed in pairs at the inside portion thereof which corresponds to a rear glass substrate 113. The row electrodes are covered by a dielectric layer 111. An MgO (magnesia) layer 112 is deposited on the dielectric layer 111 by vacuum deposition. Between the MgO layer 112 and the rear substrate 113, a discharge space 114 is formed. The pixel data electrodes D1-Dm coated with phosphor are formed on the inside portion of the rear substrate 113 to intersect the row electrodes X and Y of the front substrate 110.
A pair of row electrodes X and Y form one row of an image. At the intersection of each of the pixel data electrodes Dj (j=1,2,3, . . . m) and each pair of row electrodes Xi and Yi (i=1,2,3, . . . n), a pixel Pi,j is formed (FIG. 14).
Operation of the PDP 11 will be described. FIG. 16 shows a timing chart of drive signals for driving the PDP.
The row electrode driver 10 applies a first reset pulse RPx of positive voltage to each of the row electrodes X1-Xn and a second reset pulse RPy of negative voltage to each of the row electrodes Y1-Yn. Thus, the row electrodes in pairs are excited to discharge, thereby producing charged particles in the discharge space 114 at the pixel Pi,j. Thereafter, when the discharge is finished, a predetermined amount of wall charge is uniformly formed on the dielectric layer 111 at the pixel Pi,j (A reset period all at once).
The pixel data electrode driver 12 applies pixel data pulses DP1-DPn of positive voltage corresponding to the pixel data for every row to the pixel data electrodes D1-Dm in order.
At that time, the row electrode driver 10 applies the scanning pulses SP each of which has a small width to the row electrodes Y1-Yn in order in synchronism with the timings of the data pulse DP1-DPn. The driver 10 further applies the priming pulses PP of positive voltage to the row electrodes Y1-Yn, immediately before the scanning pulses SP.
In the discharge space 114, the charged particles obtained by the operation of reset all at once are reduced as the time passes. Therefore, the priming pulse PP is applied to the row electrodes for reproducing the charged particles in the discharge space 114.
The writing of the pixel data is performed in accordance with the scanning pulse SP in existence of the charged particles. For example, when the logic value of the pixel data is "0", the scanning pulse SP and the pixel data pulse DP are simultaneously applied, so that the wall charge produced in the pixel is disappeared. On the other hand, when the logic value of the pixel data is "1", only the scanning pulse SP is applied, so that the discharge does not occur. Thus, the wall charge in the pixel is held, thereby emitting light. Namely, the scanning pulse SP is a selecting and erasing pulse for selectively erasing the wall charge as a trigger in accordance with the pixel data (An address period).
The row electrode driver 10 continuously applies the sustaining pulse IPx of positive voltage to the row electrodes X1-Xn and the sustaining pulse IPy of positive voltage to the row electrodes Y1-Yn at offset timing from the sustaining pulses IPx. During the sustaining pulses are applied, the pixel which hold the wall charge sustains the discharge and emission of light (A discharge sustaining period).
Then, the driver 10 applies the erasing pulses EP to the row electrodes Y1-Yn, thereby erasing the wall charge (A wall charge erasing period).
From the foregoing, in the display system, the reset pulses are applied to the row electrodes to reset them all at once. Thereafter, the priming pulse and the scanning pulse are sequentially applied to the row electrodes for reproducing the charged particles in the discharge space 114 and writing the pixel data for every row.
Thus, the time for operating every row is equal at a high speed. Furthermore, since the pixel data is written in every row in accordance with the scanning pulse SP during the charged particles exist in the discharge space 114. The writing of the pixel data is accurately performed.
As shown in FIG. 16, the priming pulse PP of the positive voltage and the scanning pulse SP of the negative voltage are applied to the row electrode Y.
However, in the system, two pulses having a different polarity are scanned in the row electrodes in pairs. If an all-purpose IC for driving the row electrode driver 10 is used as the row electrode driver, only one pulse having a single polarity can be scanned. The all-purpose IC for scanning two different pulses has not been known at present.
In order to obtain a display having a high definition, the number of row electrodes and the number of tones must be increased, and a scanning rate (address writing cycle) must be reduced. For example, if a display having 1000 rows and 256 tones (8-bit pixel data) is obtained such as a high definition television (HDTV), the scanning rate is about 2 .mu.s (microsecond: 10.sup.-6 seconds). Such a system is liable to produce error discharge. As a result, it is difficult to stabilize a display operation.